Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer to join their Next Generation, High-Speed Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team. The role focuses on the architecture, design, and deployment of high-speed memory subsystems in QCT products. The engineer will work on enabling high-speed designs, developing architecture and design specifications, and collaborating with verification engineers to ensure high-quality results. This position requires a strong background in ASIC design and hardware architecture.

• Bachelor's or Master's degree in Science, Engineering, or a related field.
• 5+ years of ASIC design, RTL coding, and front-end digital design experience.
• 3+ years of Hardware Architecture experience.
• Experience with LPDDR memory and cache controller, NoC based architectures, and front-end interfacing to CPUs, DSPs, and multimedia processors.
• Exposure to HBM memory type designs and on-chip tightly coupled SRAM & L3 cache controller architecture/design.

• Enable high-speed (1GHz+) designs in QCT products.
• Develop and contribute to architecture and design specifications.
• Drive the micro-architecture of portions of the logic design.
• Implement and deliver RTL and collaborate with verification engineers.
• Debug designs and provide support when integrated into the rest of the chip.
• Contribute to the overall improvement in design methodology to enhance productivity and quality.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.