Qualcomm is seeking a motivated ASIC front end design engineer to join their high-speed parallel interfaces team. This role involves working with a global team to architect, design, and implement DDR and die-2-die interfaces. The engineer will focus on designing and developing RTL for digital IPs that connect SoCs to DRAM devices. Collaboration with systems architecture, verification, timing, and physical design engineers is essential to ensure successful implementation and silicon bring up.

• Bachelor's degree in Science, Engineering, or related field.
• Minimum of 4 years of ASIC design, verification, or related work experience.
• Experience in high-speed, low power digital logic design development.
• Hands-on experience with ASIC front end implementation tool flow methodologies.

• Design and develop RTL for digital IPs serving systems connecting SoCs to DRAM devices.
• Implement control and data-path blocks for SoC interfaces.
• Work closely with cross-functional teams to enable all phases of implementation and silicon bring up.
• Conduct gate level simulation debug and low power implementation and sign off.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.