This role at Qualcomm involves leading and planning the timing analysis of complex sub-systems within System-on-Chips (SoC). The individual will work on premium tier chips utilizing advanced technology nodes such as 14nm, 5nm, 34nm, and 3nm. The position requires expertise in SoC design architecture and timing signoff processes. The candidate will also mentor junior team members and collaborate with multiple teams to ensure timing closure across various operating modes.

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Seven years of progressive experience in a related occupation

• Lead and synthesize ambiguous or conflicting requirements for timing analysis.
• Perform constraint validation at various levels of design stages.
• Conduct various clock tree analyses and early planning of pipelines for critical interface timing closure.
• Develop multiple flow/scripts for easy access to timing reports.
• Mentor and train junior team members.
• Perform correlation activities between PNR tool and timing signoff tools.
• Generate ECOs for various subsystems.
• Act as a strong contributor at design reviews and project meetings.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.