The role involves leading the Physical Design Flow for high-speed DDR and graphics in SoC products at Qualcomm. The individual will synthesize complex requirements and focus on power utilization and optimization. This position requires collaboration with cross-functional teams to ensure successful project execution and signoff closure for tapeout. The candidate will also participate in design reviews and communicate development plans effectively.

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with three years of experience in a related occupation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with seven years of progressive experience in a related occupation.
• Any suitable combination of education, training, or experience will be accepted.

• Lead floor planning, clock tree synthesis, place and route, PDN, and timing analysis and closure.
• Perform various physical verification checks such as LVS, DRC, design-for-manufacturing, and design-for-yield at the chip and block levels.
• Provide schedules and support cross-functional engineering efforts to drive signoff closure for tapeout.
• Act as a strong contributor in design reviews and project meetings.
• Communicate and implement a development plan effectively.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.