The role involves working with the NoC bus team at Qualcomm, which focuses on the development and analysis of bus components for system-on-chips (SoCs). The team is responsible for identifying architecture bottlenecks and making micro-architecture choices based on performance and power analysis. Candidates will need to collaborate with various teams to ensure successful deployment of interconnects and provide design guidelines for bus protocol compliance. Strong knowledge of bus protocols and ASIC design is essential for this position.

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design experience, or a Master's degree with 5+ years of experience, or a PhD with 4+ years of experience.
• Strong knowledge of bus protocols such as AHB, AXI, and CHI.
• Experience with synthesis tools, process nodes, and VLSI design.
• Ability to define bus components micro-architecture with knowledge of performance, power, and area tradeoffs.
• Excellent communication skills and the ability to adapt to changes.

• Create micro-architecture bus components specifications and analyze performance results.
• Deliver RTL and run tool flows for the SoC team.
• Evaluate new IPs and drive new protocol deployments.
• Define system-wide guidelines for IPs to inter-operate within the SoC.
• Support verification and silicon validation teams.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.