Qualcomm is seeking a candidate for the Digital ASIC Design Team to focus on the implementation and verification of advanced DFT/DFD techniques for low power, multi-voltage designs. The role involves deploying methodologies that enhance product quality and yield learning on cutting-edge process technologies. The ideal candidate will have extensive hands-on experience with industry-standard DFT techniques. This position emphasizes the importance of diversity and inclusion within the team and the company.

• 10+ years of industry experience in the implementation and verification of advanced DFT/DFD techniques for low power and multi-voltage domain designs.
• A strong fundamental knowledge of DFT is required.
• Understanding of core-based test methodology and scan isolation.
• Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
• Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation, and at-speed testing.
• Experience with industry EDA ATPG and insertion tools.
• Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, and coverage analysis.

• Implement and verify advanced DFT/DFD techniques for low power, multi-voltage designs.
• Deploy DFT methodologies that reduce test costs and increase product quality.
• Conduct DFT pattern generation, coverage analysis, and debugging.
• Run and debug gate level simulations.
• Support diversity and inclusion within the team and the company.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.