The role involves designing adaptive power management controllers and digital power meters for wireless SoC chips. The engineer will work closely with various teams, including technology/circuit design and verification, to ensure successful implementation of low power features. The position requires a strong understanding of ASIC design processes and methodologies, as well as collaboration with system and software teams to enable functional safety features. The engineer will also analyze power models and methodologies throughout the design cycle.

• 3 years of experience in low power digital ASIC design.
• Familiarity with ASIC front-end design processes, including RTL coding and simulation.
• Proficiency in scripting languages such as Python, Perl, and TCL.
• Understanding of electrical engineering concepts and circuit analysis.

• Design adaptive power management controllers and on-chip sensor controllers.
• Perform RTL design, simulation, synthesis, and timing analysis for IP blocks.
• Collaborate with technology and circuit design teams to finalize IP block specifications.
• Support the SoC team in integrating low power solutions into wireless SoC chips.
• Create and enhance low power methodologies covering the entire design cycle.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.