The role of CPU Physical Design Timing Engineer at Qualcomm involves defining, developing, and driving CPU timing closure for Oryon CPU Cores. The engineer will collaborate with microarchitecture and RTL design teams to develop timing constraints and implement designs that meet power, area, and performance goals. This position offers the opportunity to work with industry-leading technology nodes and contribute to multiple CPU projects. The engineer will also be responsible for coding scripts for STA tools and enhancing CPU timing infrastructure.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant work experience, or a Master's degree with 1+ year of experience, or a PhD in a related field.
• Excellent automation skills using TCL, Perl, or Python.
• Strong expertise in STA timing analysis basics and timing methodologies.

• Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
• Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Identify root causes of timing miscorrelation at different design levels and propose solutions.
• Evaluate multiple timing methodologies and tools on different designs and technology nodes.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.