The role at Qualcomm Technologies, Inc. involves leading the Physical Design Flow for high-speed DDR and graphics in system-on-chip (SoC) products. The individual will focus on optimizing power utilization and performance while managing complex requirements. This position requires collaboration across engineering teams to ensure successful tapeout signoff. The candidate will also participate in design reviews and project meetings to communicate and implement development plans.

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with three years of experience in a related occupation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with seven years of progressive experience in a related occupation.
• Any suitable combination of education, training, or experience will be accepted.

• Lead floor planning, clock tree synthesis, place and route, PDN, and timing analysis and closure.
• Perform various physical verification checks such as LVS, DRC, design-for-manufacturing, and design-for-yield at chip and block levels.
• Provide schedules and support cross-functional engineering efforts to drive signoff closure for tapeout.
• Act as a strong contributor in design reviews and project meetings.
• Communicate and implement a development plan.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.