As an ASIC Design Verification Engineer at Qualcomm, you will be part of a team responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. Your role will focus on comprehensive pre-silicon test planning for digital power IPs and developing testbenches using advanced verification methodologies like SystemVerilog-UVM. You will also work on improving verification efficiency through automation and engage in power-aware UPF verification flows. This position requires inventive minds to help transform the potential of 5G into world-changing technologies.

• Minimum 3 years of DV experience using UVM/assertion based verification technologies
• Experience in verifying complex SOC or SOC subsystems
• Experience with caches and DDR memory protocol verification
• Exposure to firmware/driver development using C++
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, or a Master's degree with 1+ year of experience, or a PhD in a related field

• Develop comprehensive pre-silicon test plans for digital power IPs
• Create testbenches using advanced verification methodologies such as SystemVerilog-UVM
• Engage in coverage development, assertion model development, and formal verification
• Learn and deploy power-aware UPF verification flow and methodology
• Develop automation to improve verification efficiency

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.