Qualcomm's DSP Team is looking for talented Physical Design Engineers to join their DSP PD team. The role focuses on innovating, developing, and implementing DSP cores using advanced tools and technologies. Candidates will need strong expertise in physical design flow, tapeout readiness, and PPA optimization for advanced technology nodes. This position offers the opportunity to work on cutting-edge designs and collaborate with various teams to influence design decisions.

• Bachelor's or Master's degree in Electrical Engineering or a related field.
• 3+ years of industry experience in Physical Design for ASIC/SoC.
• Proven tapeout experience with successful delivery of complex cores.
• Hands-on expertise with Place & Route tools such as Cadence Innovus and/or Synopsys ICC2/Fusion Compiler.
• Strong understanding of DFT, multi-mode/multi-corner designs, and ECO flows.
• Proficiency in scripting languages including Perl, TCL, and Python, as well as Linux/Unix environments.

• Own and execute the complete Physical Design flow from netlist to GDSII.
• Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
• Develop and enable low-power implementation methods and customized P&R strategies.
• Debug timing violations, implement timing fixes, and roll in functional ECOs.
• Conduct RC extraction, signal integrity, crosstalk noise/delay analysis, and formal verification.
• Manage tapeout activities, ensuring sign-off for DRC, LVS, timing, power integrity, and reliability.
• Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
• Contribute to flow enhancements and automation using scripting.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.