As a Physical Design Clock Engineer at Qualcomm, you will collaborate with microarchitecture, RTL design, and physical design teams to develop advanced clocking solutions for next-generation CPUs. This role focuses on creating efficient clock generation and distribution methodologies while ensuring low skew and low power consumption. You will leverage your expertise in device physics and circuit design to optimize clocking techniques. The position is available in both Austin and Santa Clara, with compensation adjusted based on location.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience, or a Master's degree with 3+ years, or a PhD with 2+ years.
• Experience in clock H-tree, mesh, spines, and CTS implementations.
• Proficiency in SPICE simulation and analysis for circuit design and verification.
• Good understanding of device physics, RC delay, and electrical aspects.
• Experience in chip physical design and standard cell optimizations.

• Work with design teams to understand, implement, and validate CPU clocking.
• Drive overall clock generation and distribution methodology of CPU.
• Collaborate with CAD and block level designers to implement clocking techniques for optimizing skew and power.
• Perform jitter analysis and measurements.
• Provide feedback to block level and top level physical design engineers on key fixes required.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.