Qualcomm Atheros is seeking a key member for its Integrated Wireless Technology team, focusing on WiFi technology and SOC infrastructure. The role involves hands-on micro-architecture, RTL design, and full-chip integration throughout the ASIC lifecycle. Candidates will work closely with various subsystem teams to ensure smooth integration of releases. This position requires a strong background in ASIC design and verification methodologies.

• 5+ years of industry experience in ASIC design, micro-architecture, and design integration.
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design experience, or a Master's degree with 1+ year of experience, or a PhD.
• Strong background in SoC micro-architecture, including specification, definition, and implementation of functional blocks.
• Hands-on experience with multi-domain clocking implementation in SOCs.
• Proficiency in Python/Perl.

• Be responsible for micro-architecture, RTL design, and development of new functional blocks.
• Oversee subsystem and full-chip integration.
• Own the design through the complete ASIC lifecycle, from concept through tape-out.
• Collaborate closely with other subsystem teams to ensure smooth integration of releases.
• Interface with verification, DFT, FPGA emulation, and implementation teams.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.