The Sr. Package Layout Engineer at Annapurna Labs will lead the physical design of advanced IC packages for machine learning and data center ASICs. This role involves managing the package layout from initial planning through to manufacturing release, ensuring designs meet performance and reliability targets. The team values mentorship and knowledge-sharing, fostering an environment for career growth and technical expertise development. The engineer will collaborate with various teams to optimize designs and drive innovation in packaging technologies.

• Bachelor's degree in Electrical Engineering or a related field
• 10+ years of experience in IC package layout and physical design
• Proven track record of leading package designs from concept through tape out for complex, multi-layer organic substrates or silicon interposers
• Hands-on expertise with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent
• Deep understanding of advanced packaging technologies: 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbump, and silicon bridge interconnects
• Strong knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks)
• Experience with bump map and ball map definition, escape routing strategies, and power/ground plane design for high pin-count packages
• Familiarity with substrate and interposer manufacturing processes, material properties, and their impact on design decisions

• Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
• Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies.
• Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal escape routing, and decoupling capacitor placement.
• Perform detailed RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates and silicon interposers.
• Participate in die-level RDL routing and bump planning in coordination with ASIC physical design teams.
• Drive cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels.
• Develop and maintain package stack-up definitions in collaboration with SI/PI and materials engineering teams.
• Create and enforce package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance and high yield.
• Run and review physical verification checks and drive design closure with zero escapes.
• Manage package design schedules, milestones, and deliverables, coordinating across multiple concurrent projects and tape out cycles.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout.
• Interface with OSAT vendors and foundry partners on substrate and interposer manufacturing feasibility.
• Identify packaging technology risks early and propose design or process mitigations.
• Mentor junior layout engineers and contribute to the development of team best practices.

• Employees at Amazon are often offered comprehensive health benefits—including multiple medical plan options (no pre-existing condition exclusions, 100% covered in-network preventive care), dental and vision plans, a 24/7 medical advice line from day one, expert second-opinion services, and broad mental-health support with several free counseling sessions (including pediatric). Financial wellness typically includes a 401(k) with company match (up to 2%), Restricted Stock Units (equity), FSAs, an emergency savings program, product and partner discounts, and even college-savings and home-purchase programs. Overall, the package is designed to support employees and their families’ health, finances, and day-to-day life.