The TPU SoC Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration. The engineer will work on the design and implementation of custom silicon solutions for Tensor Processing Units (TPUs) that power Google's AI applications. This position involves collaboration with various ASIC development teams and requires expertise in digital logic design and RTL coding. The role offers the opportunity to address challenging technical problems in a dynamic and innovative environment.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 2 years of experience architecting RTL solutions using software-based construction.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

• Define and document the microarchitecture for digital designs within the TPU.
• Develop high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Partner with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.