The Senior ASIC Physical Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom silicon solutions, particularly Tensor Processing Units (TPUs). The position involves collaboration with various teams to optimize performance, power, and area in design. The engineer will contribute to both the physical design of complex blocks and the full chip closure process. This role is critical in driving innovation and ensuring the integration of advanced technology within AI/ML systems.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience with physical design from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure.
• Experience in Python, Tcl, or Perl scripting.
• Experience working with external partners on Physical Design closure.
• Experience in Static Timing Analysis with an understanding of timing corners, margins, and derates.

• Participate in the Physical Design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL to GDS.
• Collaborate with internal logic and internal and external teams to achieve optimal Power/Performance Analysis.
• Conduct feasibility studies for new microarchitectures and optimize runs for finished RTL.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.