Qualcomm Atheros is seeking an experienced Static Timing Analysis (STA) and Synthesis Engineer to join their Integrated Wireless Technology team. This role focuses on driving timing-critical implementation for high-performance, low-power Wi-Fi solutions across various platforms. The engineer will collaborate closely with multiple teams to ensure high-quality silicon delivery on aggressive schedules. The position involves ownership of static timing closure and synthesis for complex low-power Wi-Fi SoCs and sub-systems.

• 6–8 years of experience in ASIC/SoC STA, synthesis, timing constraint development, low power checks, and functional ECO implementation.
• Deep knowledge of Static Timing Analysis (STA) and timing constraints.
• Experience with Multi Mode Multi Corner (MMMC) timing closure and advanced technology nodes.
• Experience in Synthesis and Logical Equivalence Checking (LEC).
• Scripting skills in TCL and Perl.

• Drive subsystem-level STA and timing closure for both pre-layout and post-layout phases.
• Perform timing analysis using PrimeTime and contribute to full-chip signoff activities.
• Identify timing bottlenecks, debug violations, and recommend optimizations.
• Develop and validate SDC constraints for accurate STA analysis.
• Collaborate with RTL, synthesis, and physical design teams to ensure robust timing closure.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.