The Design-for-Test Engineering team at NVIDIA focuses on innovative solutions for DFT architecture, verification, and post-silicon validation of complex semiconductor chips. As a team member, you will collaborate with cross-functional teams to implement advanced designs in test access mechanisms and BIST. The role also involves mentoring junior engineers and developing methodologies for next-generation products. This position is ideal for engineers passionate about technology and eager to tackle challenging problems.

• BSEE or equivalent experience with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains.
• Demonstrated knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
• Excellent analytical skills in verification and validation of test patterns on complex designs.
• Good exposure to cross-functional areas including RTL design, STA, place-n-route, and power.
• Experience in Silicon debug and bring-up on ATE with an understanding of pattern formats and test program development.
• Strong programming and scripting skills in Perl, Python, or Tcl.
• Extraordinary written and oral communication skills.

• Own and work with cross-functional teams to implement state-of-the-art designs in test access mechanisms.
• Help develop and deploy DFT methodologies for next-generation products.
• Mentor junior engineers on test designs and trade-offs including cost and quality.

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.