As a member of the Infinity Fabric Architecture and RTL team at AMD, you will design and implement key components of a scalable, coherent on-chip network that facilitates high-speed communication across CPUs, GPUs, and accelerators. This role emphasizes defining microarchitecture and developing RTL for interconnect subsystems that support various products, including servers and AI platforms. You will collaborate with cross-functional teams in a fast-paced environment to deliver high-quality, performance-optimized hardware. Your work will contribute to shaping the future of computing experiences.

• Experience with RTL design using Verilog or SystemVerilog
• Background in interconnect, network-on-chip (NoC), or cache/memory subsystem design
• Understanding of processor architecture, including coherency and memory systems
• Knowledge of digital design fundamentals and high-speed hardware systems
• Experience debugging RTL or hardware systems
• Familiarity with power, performance, and area tradeoffs
• Exposure to scripting or programming languages such as Python, C, or C++
• Awareness of design-for-test (DFT) concepts
• Familiarity with x86 or ARM architectures is helpful
• Interest in using AI-assisted tools to improve design and debugging workflows

• Define microarchitecture for interconnect components
• Develop and implement synthesizable RTL using Verilog/SystemVerilog
• Optimize designs to meet power, performance, area, and timing goals
• Contribute to scalable, coherent interconnect solutions across multiple product lines
• Collaborate with architecture, verification, and cross-functional engineering teams
• Support unit-level validation and deliver high-quality RTL to verification teams
• Develop assertions and contribute to coverage strategies
• Debug design issues during pre-silicon and post-silicon phases
• Create clear and maintainable design documentation

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.