As a Physical Design Timing Engineer at Intel, you will be instrumental in delivering next-generation System-on-Chip (SoC) products. Your role will focus on optimizing timing, power efficiency, and performance of advanced designs. You will collaborate with cross-functional teams to develop methodologies and solutions that address complex technical challenges. This position offers an opportunity to shape the future of computing through innovative product development.

• Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 12 years of experience with a Bachelor's degree, 8 years with a Master's degree, or 6 years with a PhD in timing analysis, physical design, or a related domain.
• Proficiency in static timing analysis, timing constraint generation, and timing optimization techniques.
• Experience with tools, flows, and methodologies for physical design and timing analysis.
• Strong knowledge of SoC clocking, timing budgeting, and constraint adaptation.
• Familiarity with scripting languages such as TCL for automation and design optimization.
• Understanding of digital design fundamentals, power and performance analysis, and optimization techniques.

• Perform comprehensive timing analysis and optimization to ensure robust, high-performance designs.
• Generate and validate timing constraints and address timing violations at the chip and block levels for SoCs.
• Conduct timing rollups and ensure functionality of designs with optimized performance and power characteristics.
• Develop and implement methodologies to produce high-quality timing models that enhance the efficiency of the physical design team.
• Define process, voltage, and temperature (PVT) conditions tailored to product operating plans and binning requirements for precise timing analysis.
• Collaborate with clocking teams and full-chip designers to maintain clocking balance, resolve timing issues, and optimize power delivery and partitioning.
• Partner with architecture, clocking design, and logic design teams to define and validate advanced SoC clocking flows and methodologies.
• Ensure adherence to high-performance, low-power clock network guidelines while driving flow development for seamless chip integration.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.