JobsSenior ASIC Design Engineer - DFX
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Senior ASIC Design Engineer - DFX

NVIDIA

Location

Santa Clara, CA

Type

Full-time

Posted

7/11/2026

Compensation

$168,000 - $310,500 per year

Undergraduate with 5+ Years of Experience
Master's with 5+ Years of Experience
Approval 99.2%·Filings 1,781·New hires 873·
👑 Elite Sponsor
·FY 2025

Job description

The Senior ASIC Design Engineer - DFX at NVIDIA will be a key member of the DFX Methodology Team, focusing on the architecture, design, implementation, and verification of DFT IPs for next-generation SoC products. This role involves driving innovation throughout the silicon lifecycle and mentoring junior engineers. The position requires collaboration with various teams to ensure cohesive integration and successful post-silicon validation. Candidates will have the opportunity to work on complex semiconductor designs that impact various industries.

Requirements

  • Bachelor's degree or equivalent experience with 8+ years of experience, or a Master's degree in Electrical Engineering or related field with 6+ years of experience.
  • 5+ years of hands-on experience in SoC architecture, RTL design, and verification.
  • Strong proficiency in micro-architecture and RTL development using Verilog.
  • Deep expertise in DFT design, methodology, and implementation.
  • Familiarity with related domains such as clocking, STA, place & route, and power optimization.
  • Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.
  • Proficiency in scripting languages such as Python, Perl, or Tcl.
  • Excellent communication skills and a collaborative mindset.

Responsibilities

  • Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
  • Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
  • Define and align feature sets by working closely with architects, platform, and software teams.
  • Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
  • Create and execute test plans to support both functional and DFT full-chip verification.
  • Support post-silicon bring-up and validation efforts including debug and issue resolution.
  • Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

Benefits

  • Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.

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