The role involves joining Qualcomm's Global CAD team to enhance gate-level synthesis and DFT stitch solutions for Snapdragon chips. Candidates will work closely with design and implementation teams to develop methodologies and tools aimed at improving performance, power, and area (PPA) while reducing design cycle times. The position requires experience in synthesis, DFT, and CAD development, utilizing both internal and EDA technologies. The team is focused on innovation in automation and methodologies for complex designs.

• Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, or a related field.
• 5-10 years of experience in VLSI CAD, preferably in Synthesis, DFT, and Place & Route.
• 5-10 years of experience with scripting tools and programming languages, preferably Python and TCL.
• 6+ years of ASIC design, verification, validation, or integration experience for a Bachelor's degree holder, or 5+ years for a Master's degree holder, or 4+ years for a PhD holder.

• Participate in the development of Qualcomm DFT stitch flow and methods.
• Improve SoC Synthesis and DFT Stitch methodologies for various Snapdragon chips.
• Enable new features from EDA tools or internal tools for Synthesis and DFT Stitch checks.
• Develop and support methodologies to handle complex multi-voltage crossings on DFT paths.
• Support Snapdragon design teams on CAD solutions and address their requests through ticket queues.
• Interface with EDA vendors to enable production-ready tool sets.
• Set up, augment, and maintain a regression of complex DFT Stitch and Synthesis test cases.
• Innovate with design, tool, and flow techniques for area reduction and dynamic power reduction.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.