This position involves developing logic design, RTL coding, and simulation for mixed-signal IPs, focusing on generating cell libraries and functional units for full chip designs. The role requires collaboration with various design teams to ensure high-quality integration of IP blocks. The team is part of Intel's Central Engineering Group, which emphasizes customer-driven solutions and efficient development cycles. The ideal candidate will possess strong debugging skills and a deep understanding of mixed-signal design principles.

• Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 7+ years of industry experience, or a Master's Degree with 4+ years of industry experience.
• Expert-level proficiency in Verilog / SystemVerilog for RTL design.
• Deep knowledge of RTL-to-GDSII flow, STA, and CDC.
• Experience integrating analog IP with digital logic.
• Understanding of timing, power, and performance trade-offs.

• Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation.
• Write and optimize mixed-signal logic to meet power, performance, area, and timing goals.
• Review verification plans and implementation to confirm design features are verified correctly.
• Resolve and implement corrective measures for failing RTL tests to ensure feature correctness.
• Support SoC customers to ensure high-quality integration of the IP block.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.