The Senior DFT Engineer role at Google Cloud focuses on shaping the future of AI/ML hardware acceleration through the development of cutting-edge TPU technology. The engineer will work closely with design and verification teams to ensure the quality and reliability of chip designs. This position involves driving DFT strategy and collaborating on the integration of DFT solutions within the ASIC design flow. The role is part of a team that empowers Google customers with innovative capabilities and insights.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with DFT features such as JTAG, MBIST, ATPG, and HSIO.
• Experience with scripting languages like Python, Perl, or TCL.
• Experience with ATE platforms such as Teradyne UltraFlex or Advantest.
• Experience with SystemVerilog.

• Engage with DFT and Design teams at early design stages to define requirements for ATE tests and manufacturing test flow.
• Generate and verify ATE patterns, including debug level, production level, and characterization.
• Run pattern playbacks on all delivered patterns prior to silicon arrival to ensure high quality of pattern delivery.
• Own pattern translations and integrate DFT verification into the overall ASIC design flow.
• Prepare silicon debug verification strategy, test plan, and readiness for testers.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.