The Senior ASIC DFT Engineer role at Google involves working on custom silicon solutions that enhance the performance of Google's products. The engineer will focus on Design for Test (DFT) across various aspects, from architecture to silicon debug. This position requires collaboration with multi-disciplined teams to ensure effective DFT implementation. The role aims to contribute to innovative hardware experiences that improve technology for users worldwide.

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of experience with Design for Test (DFT).
• Experience with DFT EDA Tools such as Tessent, Genus, and Fusion Compiler.
• Experience with scan insertion, Automatic Test Pattern Generation (ATPG), and silicon debug.

• Work with multi-disciplined teams of DFT engineers and product engineering.
• Develop tests for Production in the automated test equipment flow.
• Drive scan implementation and verification to ensure coverage across all fault models.
• Manage Gate-Level Simulation verification and post-silicon bring-up and debug.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.