JobsPrincipal Engineer, AMS IP Architecture
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Principal Engineer, AMS IP Architecture

Intel

Location

Santa Clara, CA, Hillsboro, OR, Folsom, CA, Austin, TX, Phoenix, AZ

Type

Full-time

Posted

7/16/2026

Compensation

$220,920 - $311,890 per year

Undergraduate with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
💎 Strong Sponsor
·FY 2025

Job description

As a Principal Engineer in AMS IP Architecture at Intel, you will be instrumental in defining and advancing next-generation analog and mixed-signal IP architectures. Your role will involve developing innovative architectures and signal processing algorithms to optimize performance across various applications. You will collaborate with cross-functional teams to ensure the delivery of exceptional AMS solutions for diverse market segments. This position is part of a cutting-edge architecture and engineering organization focused on creating industry-leading IPs.

Requirements

  • M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with a focus on high-speed communications, analog circuits, or signal processing.
  • Deep expertise in SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization, or communications theory.
  • Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher.
  • Hands-on work with SerDes transmitter and receiver architectures and equalization techniques.
  • Ability to correlate models with silicon measurements and debug discrepancies.
  • Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus.

Responsibilities

  • Architected end-to-end PCIe Gen7/Gen8 SerDes models in MATLAB/Simulink.
  • Executed 128Gbps+ link simulations to validate protocol specs and mitigate margin risks.
  • Designed real-time calibration and adaptation DSP algorithms balancing convergence speed, stability, and power.
  • Validated simulation models against lab silicon measurements and updated models iteratively.
  • Partnered with analog, digital, and hardware teams on circuit trade-offs and logic design.
  • Resolved technical field issues and performed custom link budget analyses for client configurations.
  • Evaluated early-stage protocol updates and design specs to ensure system-level feasibility.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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