The Package Design Engineer will be part of the Silicon Integration team at Google, focusing on developing advanced package substrate designs for machine learning chips. This role involves collaboration with various engineering teams to optimize designs for electrical performance and reliability. The engineer will manage the entire design process, ensuring that the package designs meet production standards. This position is crucial for enhancing Google's hardware capabilities and contributing to innovative products used by millions worldwide.

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, or a related field, or equivalent practical experience.
• 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
• Experience in chip package substrate layout, design verification, DFM, and taping out for production.
• Experience in design automation and scripting.

• Develop physical package substrate design of large form-factor packages for high-performance computers.
• Implement methodology and CAD flow for efficient substrate design and enhanced productivity.
• Manage and drive co-design initiatives across chip, package, and system levels.
• Collaborate closely with signal integrity/power integrity, thermal, and mechanical engineering teams.
• Define and document the requirements for the package substrate design and bill of materials.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.