Qualcomm Atheros is seeking a Physical Design Engineer to join their Integrated Wireless Technology team. This role focuses on the complete Physical Design Flow and the delivery of complex, high-speed, low power designs. The engineer will innovate and implement chips and cores using advanced tools and technologies. The position requires expertise in various aspects of physical design, including timing optimization and debugging.

• 2+ years of industry experience in tiles level or sub-system level or SoC top level physical design.
• Successful tapeout experience.
• Experience with floorplanning of macro cells.
• Proficiency in Place & Route (PNR) tools such as Cadence Innovus and/or Synopsys Fusion Compiler.
• Timing closure (STA) experience in Synopsys PTSI.
• Experience in Function ECO implementation.
• Formal verification (FV) experience.
• Power domain analysis (IR Drop/PDN) experience.
• Physical verification (PV) experience.
• Bachelor's degree in Science, Engineering, or related field.

• Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
• Involve in tiles level development and enablement of low power implementation methods.
• Customize Place & Route to achieve area reduction, performance, and power goals.
• Handle functional and test mode constraints for place and route, floorplanning, and power planning.
• Conduct IR drop analysis, routing, timing optimization, and closure.
• Implement timing fixes and functional ECOs while debugging and fixing physical violations.
• Perform formal verification of designs.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.