This role involves developing logic design, RTL coding, and simulation for mixed signal and high-speed IPs to support full chip designs. The engineer will participate in defining architecture and microarchitecture features while applying various strategies for mixed signal designs. The position requires collaboration with SoC customers to ensure high-quality integration of IP blocks. The ideal candidate will also review verification plans and implement corrective measures for RTL tests.

• Bachelor's degree with 4+ years of experience, or a master's with 3+ years, or a PhD with 1+ year of experience in Computer Science, Computer Engineering, Electrical Engineering, or a related technical discipline.
• 2+ years of experience in RTL design and coding using System Verilog and Verilog.
• Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating.
• Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
• Experience with hardware simulation tools and methodologies such as VCS/Verdi.
• Familiarity with IP environment and configuration management tools.
• Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, and Low power design.

• Develop the logic design, RTL coding, and simulation for mixed signal and high-speed IPs.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Apply various strategies, tools, and methods for mixed signal designs to optimize logic.
• Review the verification plan and implementation to ensure design features are verified correctly.
• Resolve and implement corrective measures for failing RTL tests.
• Support SoC customers to ensure high-quality integration of the IP block.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.