The TPU SoC Design Engineer role at Google Cloud focuses on shaping the future of AI/ML hardware acceleration. The engineer will work on SoC-level RTL design for data center accelerators, contributing to the development of custom silicon solutions that power Google's TPU technology. This position requires collaboration with various ASIC development teams and involves defining methodologies for efficient design environments. The role is integral to creating innovative hardware solutions that enhance Google's AI capabilities.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 2 years of experience in ASIC RTL design using SystemVerilog or Verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

• Define and document the microarchitecture for digital designs within the TPU.
• Write performant and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.