The role is part of the Design Technology Platform organization within Intel Foundry, specifically within the X-Chip SoC Full-Chip Integration team. This team is crucial for enabling semiconductor innovation by delivering testchip platforms that validate advanced process technologies. The position focuses on developing physical design methodologies and driving full-chip SoC integration for cutting-edge testchip vehicles. Collaboration across design, process, and manufacturing teams is essential to ensure high-quality solutions for advanced technology nodes.

• Master's degree in electrical engineering or related field.
• Minimum of 5 years of experience with physical/layout design in advanced technology nodes.
• Experience with layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler.
• Knowledge of design rules and layout constraints in advanced semiconductor processes.
• Experience with floorplanning, hierarchical design integration, and layout verification/debug.

• Develop layout design methodology for testchip development in next generation process nodes.
• Work closely with Process Integration, Yield, and QnR to define critical design features for early lead vehicle test chips.
• Establish and maintain hierarchical layout design specifications for correct-by-construction integration.
• Build and execute tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements.
• Drive all aspects of physical design convergence, including preparing layout hierarchy for design tape-in and resolving issues uncovered by verification tools.
• Collaborate with tool/flow owners and vendors for ongoing tool and methodology improvement.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.