The role is for a senior member of the Cores DFT Team at AMD, focusing on ATPG responsibilities for high-performance cores. The candidate will address multi-dimensional issues such as power, area, and timing to ensure high-quality design and operational efficiency. Collaboration with architecture, IP design, physical design teams, and product engineers is essential to achieve first pass silicon success. The position emphasizes innovation and a culture of collaboration within the team.

• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Experience in debugging low coverage and DRC fixes.
• Proficient in logic design using Verilog.
• Experience in debugging test pattern issues.
• Support of Silicon bringup activities.
• Experience with post-silicon debug.
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc.
• Experience with Tessent Scan/ATPG.
• Excellent presentation and inter-communication skills.
• Bachelor's degree in Electrical Engineering or Computer Engineering.

• Own the ATPG responsibilities for the next generation of AMD high-performance cores.
• Factor many multi-dimensional issues such as power, area, and timing.
• Work closely with architecture, IP design, physical design teams, and product engineers.
• Contribute to delivering a high-quality design.
• Improve AMD's operating expenses through effective design strategies.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.