Intel's HIPD team is seeking a senior Logic design engineer to contribute to the UCIE PHY IP for datacenter and server designs. The role involves developing logic design and RTL coding while ensuring quality checks for timing and power convergence. The engineer will work collaboratively across teams and geographies, applying various strategies to optimize designs. This position requires strong analytical skills and the ability to manage multiple tasks in a dynamic environment.

• Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience, or a Master's degree and 2+ years' experience, or a PhD and 1+ years' experience.
• Experience in RTL/Logic design using System Verilog Language.
• Familiarity with design of data path, power-management flow, arbitration logic, clock domain crossing, state machines, and UPF.
• Experience with front end design tools for Lint and synthesis.
• Experience with hardware simulation tools and methodologies such as VCS/Verdi.

• Develop the logic design, register transfer level (RTL) coding, and simulation for the IP block.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Perform quality checks in various logic design aspects ranging from RTL to timing and power convergence.
• Apply various strategies, tools, and methods to write RTL and optimize logic to meet design goals.
• Review the verification plan and implementation to ensure design features are verified correctly.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.