The Senior Design Verification Engineer at Google will be part of a team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role involves verifying digital logic at RTL using SystemVerilog for ASICs or FPGAs, contributing to the innovation behind products that enhance user experiences. The engineer will work on verification planning and execution, ensuring high-performance and low-power hardware. This position requires collaboration with various teams to drive coverage-driven verification strategies.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience verifying digital logic at RTL using SystemVerilog for ASICs or FPGAs.
• Experience verifying digital IP and subsystems.
• Experience working with design verification testbenches or environments.

• Develop verification plans and test plans for digital intellectual properties and subsystems.
• Create and utilize verification components and testbench environments for digital logic at RTL using SystemVerilog.
• Execute gate-level simulations and UPF-based power simulations, performing debugging to deliver high-performance and low-power hardware.
• Drive coverage-driven verification strategies to ensure complete verification closure for ASICs or FPGAs.
• Utilize scripting languages like Perl or Python to create automation and support various verification techniques.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.