The TPU RTL Design Engineer role at Google focuses on shaping the future of AI and ML hardware acceleration. The engineer will work on developing custom silicon solutions for Google's Tensor Processing Units (TPUs), which are critical for powering demanding AI applications. This position is part of a team that designs and builds hardware, software, and networking technologies to meet unique computational challenges. The engineer will leverage their expertise in ASIC RTL design to contribute to innovative products used by millions worldwide.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design, focusing on clocking, reset, or timing-critical RTL development.
• Experience with digital clock control circuits, including clock dividers, glitch-free muxes, and clock gating.
• Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automating design tasks and data analysis.

• Create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Evaluate features and their impact in collaboration with architecture and power teams.
• Create test plans to verify and debug design RTL with Design Validation teams.
• Ensure design meets physical requirements and timing closure in collaboration with physical design teams.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.