The Staff ASIC Power Engineer role focuses on shaping the future of AI/ML hardware acceleration at Google. You will work with cutting-edge TPU technology that powers Google's most demanding applications. The position involves driving power efficiency for TPU designs and contributing to the development of custom silicon solutions. You will be part of a team that pushes boundaries and innovates in the field of power management architectures.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10 years of experience in design or architecture, including logic design and power architecture.
• Experience with power design, modeling, and reduction methodologies.
• Master's degree or PhD in a relevant field is preferred.
• Experience in defining and implementing chip-wide power management architectures.

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures.
• Lead an experienced power team and own the execution and delivery of complex technical projects.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.