The Senior CPU RTL Design Engineer role at Google involves developing custom silicon solutions that enhance the performance of Google's consumer products. The engineer will work within a team that integrates AI, software, and hardware to create innovative technologies. This position focuses on CPU cache subsystems, emphasizing RTL design and microarchitecture for future CPU generations. The engineer will collaborate with various teams to ensure high-quality designs that meet performance and efficiency targets.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in the implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
• Experience with RTL language such as System Verilog and related design processes.

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.