This role is part of Apple's Silicon Technologies group, focusing on the design and manufacturing of high-performance, power-efficient processors and system-on-chip (SoC). The position involves physical verification of SoCs, ensuring that Apple products can efficiently handle complex tasks. The team collaborates closely with CAD/Technology and implementation teams throughout the chip design cycle. This highly visible role requires attention to detail and leadership in cross-functional engineering efforts.

• Bachelor's degree and 10+ years of relevant industry experience
• Experience with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows
• Knowledge of ASIC physical design and verification checks for hierarchical designs
• Scripting skills in Perl, Python, or Tcl for debugging and automation
• Familiarity with industry standard tools for physical verification such as Mentor Calibre and Synopsys ICV
• Tapeout experience with a successful track record of signoffs

• Perform various types of physical verification checks at the chip and block level
• Collaborate with CAD/Technology teams for flow bring up and validation
• Lead schedules and support cross-functional engineering efforts
• Work on padring, bump, RDL design, and collaborate with package and floorplan teams

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.