The Static Timing Analysis Engineer role at Google focuses on delivering system-on-chip (SoC) Static Timing Analysis (STA) for custom silicon solutions. This position is part of a team dedicated to developing innovative hardware experiences that enhance Google's direct-to-consumer products. The engineer will leverage their expertise in silicon timing closure and chip integration to drive performance and efficiency. This role requires collaboration with various teams to ensure the highest quality of silicon delivery.

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools such as PrimeTime or Tempus.
• Experience with STA signoff constraint authoring for full-chip level and tapeout signoff requirements.
• Experience delivering silicon.

• Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties, and their tradeoffs.
• Drive clock tree Jitter and implementation for SoCs to achieve optimal energy, performance, and area.
• Manage full chip timing constraint validation and perform full chip STA.
• Oversee final timing signoff for SoCs.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.