The RTL Design Engineer for TPU at Google will work on shaping the future of AI/ML hardware acceleration by developing custom silicon solutions for Tensor Processing Units. This role involves designing RTL Intellectual Property with a focus on management and control subsystems, while collaborating with software and system hardware teams. The engineer will contribute to the innovation behind products used by millions and will be part of a highly cross-functional team. The position requires expertise in RTL design and the ability to lead multifaceted efforts involving various stakeholders.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture is preferred.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

• Create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Collaborate with design validation teams to create test plans to verify and debug design RTL.
• Coordinate with physical design teams to ensure design meets physical requirements and timing closure.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.