Meta is seeking ASIC EDA Infrastructure Engineers to join their Infrastructure ASIC organization. The role focuses on developing and supporting EDA flows and methodologies for building System on Chip (SoC) and IP for data center applications. Candidates will work on internal tools development and automation to enhance productivity across ASIC design cycles. This position also involves collaboration with EDA vendors and managing internal EDA licenses and infrastructure.

• Knowledge of front-end and back-end ASIC tools and flows
• Experience with RTL design using SystemVerilog or other HDL
• 5+ years of experience with EDA tools and scripting languages such as Python and Tcl
• Experience with ASIC EDA infrastructure management, maintenance, and support
• Experience with developing solutions for ASIC design environments
• Experience communicating across functional internal teams and with vendors

• Develop and support front-end implementation flow
• Develop and support physical design implementation flow
• Develop and support RTL2GDS flow
• Create internal tools and automation to improve productivity across ASIC design cycles
• Collaborate with EDA vendors on new tools and technology evaluation
• Manage internal EDA license requests and installations
• Work with the internal infrastructure team on compute grid and storage management
• Adapt internal infrastructure to ASIC design solutions

• Employees at Meta are often offered comprehensive benefits, including medical/dental/vision coverage, mental-health resources, family planning support (fertility, adoption, surrogacy), and caregiving programs. Financial benefits typically include a competitive retirement plan, equity awards, life insurance, and access to financial coaching and legal support. Time-off benefits commonly feature generous PTO and holidays, unlimited sick time, various paid leaves, flexible “Global Travel Days,” and a 30-day paid break every five years.