Meta's Infrastructure Silicon team is looking for a Staff ASIC Design Verification Engineer to lead the verification strategy for custom silicon in data center infrastructure. The role involves architecting and executing end-to-end verification for complex IP blocks and SoCs, particularly for AI/ML acceleration, networking, and storage. The engineer will work closely with design, emulation, and validation teams to ensure successful silicon outcomes. This position requires a strong background in verification methodologies and collaboration across various technical teams.

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies.
• Experience in EDA tools and scripting languages such as Python, TCL, Perl, or Shell.
• Familiarity with power management verification concepts.

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on the verification test plan.
• Drive design verification to closure based on defined metrics.
• Debug and resolve functional failures in collaboration with the design team.
• Collaborate with cross-functional teams to ensure high design quality.
• Develop continuous design verification improvements using the latest methodologies and tools.

• Employees at Meta are often offered comprehensive benefits, including medical/dental/vision coverage, mental-health resources, family planning support (fertility, adoption, surrogacy), and caregiving programs. Financial benefits typically include a competitive retirement plan, equity awards, life insurance, and access to financial coaching and legal support. Time-off benefits commonly feature generous PTO and holidays, unlimited sick time, various paid leaves, flexible “Global Travel Days,” and a 30-day paid break every five years.