This position involves defining and documenting verification strategies for pre-silicon design, focusing on optimal methodologies. The role requires collaboration with both analog and digital teams, ensuring effective integration and validation processes. Candidates will architect testbenches and develop verification approaches using UVM or formal methods. The position is based in Folsom, California, and offers a hybrid work model.

• Bachelor's degree with 10+ years of relevant industry experience, or a Master's degree in a related field with 8+ years of relevant industry experience.
• 8+ years of experience with IP/SoC pre-silicon validation and coding using SystemVerilog.
• Experience with hardware simulation tools and methodologies such as VCS/Verdi.
• Proficiency in UVM methodology.

• Define, architect, and document verification strategy and methodologies for implementing and verifying pre-silicon design.
• Architect testbenches and develop Universal Verification Methodology (UVM) or formal-based verification approaches.
• Integrate block testbenches in chip-level UVM environments and verify integration.
• Develop test strategy, testbench architecture, and test plans for design blocks to conform to specifications.
• Collaborate with architecture and design teams to create random test generation plans and run functional simulations.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.