The Senior Performance Co-design Engineer for LLM Training at Google will focus on optimizing custom AI silicon for next-generation machine learning models. This role is part of the TPU Chip Architecture and Performance Co-design team, which aims to enhance hardware and software architectures for training advanced AI models. The engineer will analyze training workloads and collaborate with ML research and compiler teams to improve training algorithms. This position is pivotal in shaping the future of Google's AI capabilities and infrastructure.

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field or equivalent practical experience.
• 5 years of experience in performance modeling, computer architecture, or hardware/software co-design.
• Experience with programming in C++ or Python.

• Lead hardware/software co-design and performance modeling for LLM training workloads across current and future generation silicon.
• Analyze distributed training bottlenecks for massively scaled first-party and third-party models.
• Build and enhance modeling infrastructure, simulators, and performance tooling tailored to distributed ML training.
• Drive data-backed decisions that influence the roadmap for future TPU and Cloud Silicon architectures.
• Work closely with ML research and compiler teams to optimize training algorithms and influence future hardware design.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.