The TPU SoC Integration Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom silicon solutions. This position is part of a team that drives TPU technology, which powers Google's demanding AI/ML applications. The engineer will manage advanced multi-chiplet SoC integration projects, collaborating closely with various teams to ensure robust system designs. The role requires expertise in ASIC design and integration, with a strong emphasis on cross-domain collaboration and innovative problem-solving.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC design or RTL design.
• Experience with SoC design and integration.
• Experience with multi-chiplet SoC integration.
• Experience with SoC Design for Testing (DFT) planning.
• Experience scripting in Python, Perl, or Tcl.

• Lead advanced SoC integration projects from concept to final delivery, managing project milestones, deliverables, and cross-functional schedules.
• Partner with ASIC teams on complex interposer and package design, and resolve multi-die physical design challenges leveraging 3DIO and domain partitioning expertise.
• Utilize software-based construction to seamlessly integrate SoC IPs and maintain complete ownership of the upper-level RTL hierarchy up to the package level.
• Collaborate closely with Verification and Emulation teams to resolve complex connectivity issues and optimize system compilation.
• Participate in critical layout design decisions and SoC-level sign-off activities to ensure robust, high-performance silicon delivery.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.