The Senior Performance Co-Design Engineer for LLM Serving at Google focuses on optimizing the serving performance of large language models on custom hardware. This role is part of the TPU Chip Architecture and Performance Co-design team, which aims to enhance Google's AI silicon for next-generation machine learning models. The engineer will collaborate closely with hardware architects and model researchers to influence architectural improvements and drive data-backed decisions for future TPU/Cloud Silicon architectures. This position is crucial for shaping the future of enterprise AI and delivering advanced capabilities to Google Cloud customers.

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 5 years of experience in performance modeling/engineering, computer architecture, co-design, or systems engineering.
• Experience programming in C++ or Python.
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science is preferred.
• Experience with hardware/software co-design problems, especially performance analysis at the pre-silicon stage.

• Conduct comprehensive serving performance studies on current and emerging large language models.
• Develop and maintain advanced simulation, profiling, and modeling tools to identify bottlenecks and understand key characteristics.
• Partner with model researchers and software and hardware teams to co-design architectural improvements for LLM inference latency and throughput.
• Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.