The Senior TPU Design Engineer role at Google focuses on developing custom silicon solutions that enhance the performance of Google's products. The engineer will work within a team that integrates AI, software, and hardware to create innovative technologies. This position emphasizes the design and development of Machine Learning IPs for silicon SoCs, contributing to the next generation of hardware experiences. The ideal candidate will leverage their expertise in RTL design and microarchitecture to drive projects forward.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine Learning processors and accelerators along with specification of data flows and integration requirements.
• Drive RTL development and debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.