The RTL Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of Tensor Processing Units (TPUs). The engineer will work within a team dedicated to designing and implementing custom silicon solutions that enhance Google's AI capabilities. This position requires collaboration with various teams to ensure the successful integration of digital logic blocks within the TPU architecture. The engineer will leverage their expertise in digital logic design and RTL coding to create innovative hardware solutions.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in ASIC RTL design, focusing on clocking, reset, or timing-critical RTL development.
• Design experience optimizing for performance, power, and area.
• Experience with digital design fundamentals and microarchitecture design.
• Experience working cross-functionally with design verification and physical design teams.

• Define and document complex microarchitecture for the TPU, writing high-quality, performant, and power-efficient RTL code primarily in SystemVerilog.
• Partner with cross-functional teams to drive block-level and chip-level integration efforts for the machine learning accelerators.
• Collaborate closely with the verification team to develop robust test plans, debug RTL, and guarantee overall functional correctness.
• Support post-silicon validation and debugging efforts while contributing to the continuous enhancement of internal design tools, flows, and methodologies.
• Work closely with the physical design team to meet timing, area, power, and manufacturability requirements.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.