The Senior ASIC Design Engineer will be part of the Next Generation, High-Speed Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team at Qualcomm. This role focuses on the architecture, design, and deployment of high-speed memory subsystems for QCT products. The engineer will be responsible for enabling high-speed designs and will work closely with verification engineers to ensure high-quality outputs. Key tasks include debugging designs, synthesis, timing closure, and power analysis.

• Bachelor's or Master's degree in Science, Engineering, or a related field.
• 5+ years of ASIC design, RTL coding, and front-end digital design experience.
• 3+ years of Hardware Architecture experience.
• Experience with LPDDR memory and cache controllers.
• Exposure to HBM memory type designs.

• Develop architecture and design specifications for high-speed memory subsystems.
• Implement and deliver RTL designs.
• Collaborate with verification engineers to ensure design quality.
• Debug designs and provide support during integration.
• Contribute to the improvement of design methodology to enhance productivity and quality.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.