The Mempath Architect role at Google focuses on developing custom silicon solutions for consumer products. This position involves shaping the architecture of DRAM memory sub-systems and controllers, ensuring alignment and optimization across these tightly coupled systems. The role requires collaboration with hardware designers, validation teams, and software architects to innovate memory system technologies. The successful candidate will contribute to the next generation of hardware experiences that enhance performance and efficiency.

• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent practical experience.
• 15 years of industry experience in memory controller architecture, micro-architecture, or ASIC design.
• Experience in architecture, micro-architecture, and design of DRAM memory controllers.
• Experience in ASIC architecture performance analysis, performance tools, and simulator development at different abstraction levels.

• Define and maintain the end-to-end architectural strategy across memory sub-systems and memory controllers for consumer SoCs.
• Lead performance, power, and area trade-off analyses, feature design, clocking, and power state management across memory IPs.
• Author comprehensive hardware architectural specifications, system-level design requirements, and programmer guides for next-generation memory controllers.
• Evaluate architectural choices by developing C-models, executing workload simulations, and collaborating with verification and emulation teams.
• Serve as the primary technical contact for memory path latency, power optimization, and performance across cross-functional engineering teams.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.